Manufacturing method of semiconductor device

ABSTRACT

A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base material with an interface layer film of silicon dioxide sandwiched therebetween, and a metal gate electrode containing fluorine is further formed thereon. A heat treatment apparatus radiates flash light from a flash lamp to the semiconductor wafer in an atmosphere containing hydrogen to carry out heating treatment for an extremely short period of time of 100 milliseconds or less. As a result, diffusion of nitrogen contained in the metal gate electrode is inhibited, at the same time, only the fluorine is diffused from the high-dielectric-constant gate insulating film to an interface between the interface layer film and the silicon base material to reduce an interface state, and reliability of the gate stack structure can be improved.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a manufacturing method of asemiconductor device in which a high-dielectric-constant gate insulatingfilm is formed on a silicon substrate with an interface layer filmsandwiched therebetween.

Description of the Background Art

As a gate insulating film of a field-effect transistor (FET),application of a high-dielectric-constant film using a material having ahigher dielectric constant (high-dielectric-constant material) thansilicon dioxide (SiO2), which has been conventionally general, isstudied. The high-dielectric-constant film is being developed as a newstack structure together with a metal gate electrode using metal in agate electrode in order to solve a problem that a leak current increasesalong with advancement in thickness reduction of a gate insulating film.

There has been an attempt to introduce fluorine in order to improve theinterface characteristics of the field-effect transistor using thehigh-dielectric-constant gate insulating film. For example, JapanesePatent Application Laid-Open No. 2014-165293 discloses fluorine ionimplantation for improving a NBTI (Negative Bias TemperatureInstability) phenomenon, which occurs when a negative bias is applied toa gate. Meanwhile, Japanese Patent Application Laid-Open No. 2011-103481discloses introduction of fluorine by remote plasma treatment.

However, a method of implanting fluorine ions is effective in a case inwhich a gate insulating film is formed before a source and a drain areformed, but is inconvenient for a process of forming a gate insulatingfilm after a source and a drain are formed (so-called gate lastprocess), which has been a recent mainstream. Moreover, if fluorine isintroduced by plasma treatment, damage remains in a gate insulating filmdue to comparatively-high energy particles.

SUMMARY OF THE INVENTION

The present invention is directed to a manufacturing method of asemiconductor device of forming a high-dielectric-constant gateinsulating film on a silicon substrate with an interface layer filmsandwiched therebetween.

In one aspect of the present invention, a manufacturing method of asemiconductor device includes following steps of: (a) forming thehigh-dielectric-constant gate insulating film on a surface of thesubstrate with the interface layer film of silicon dioxide sandwichedtherebetween; (b) forming a film containing fluorine on thehigh-dielectric-constant gate insulating film; and (c) subjecting thesubstrate to heating treatment of 100 milliseconds or less to diffusethe fluorine to the high-dielectric-constant gate insulating film andthe interface layer film.

The fluorine can be subjected to heat diffusion to thehigh-dielectric-constant gate insulating film and the interface layerfilm from the film containing the fluorine, and the fluorine can beintroduced without damaging a device structure.

Preferably, in the step (c), the heating treatment of the substrate iscarried out in a gas atmosphere of one selected from a group consistingof hydrogen, ammonia, nitrogen trifluoride, and fluorine.

Diffusion control, etc. of the fluorine is enabled.

Therefore, it is an object of the present invention to introduce thefluorine without damaging the device structure.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a vertical cross-sectional view showing a configuration of aheat treatment apparatus used in a manufacturing method of asemiconductor device according to the present invention;

FIG. 2 is a perspective view showing an overall appearance of aretention unit;

FIG. 3 is a plan view of a susceptor;

FIG. 4 is a cross-sectional view of the susceptor;

FIG. 5 is a plan view of a transfer mechanism;

FIG. 6 is a lateral view of the transfer mechanism;

FIG. 7 is a plan view showing a disposition of a plurality of halogenlamps;

FIG. 8 is a diagram showing a drive circuit of a flash lamp;

FIG. 9 is a diagram schematically showing a structure of a semiconductorwafer on which a high-dielectric-constant gate insulating film isformed;

FIG. 10 is a diagram schematically showing the structure of thesemiconductor wafer on which a metal gate electrode is formed; and

FIG. 11 is a diagram for describing a phenomenon which occurs when asurface of the semiconductor wafer is subjected to flash heating.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will bedescribed in detail with reference to drawings.

First, a heat treatment apparatus which executes the heat treatmentrequired to carry out a manufacturing method of a semiconductor deviceaccording to the present invention will be described. FIG. 1 is avertical cross-sectional view showing a configuration of the heattreatment apparatus 1 used in the manufacturing method of thesemiconductor device according to the present invention. The heattreatment apparatus 1 of FIG. 1 is a flash-lamp annealing apparatuswhich carries out flash light radiation with respect to acircular-plate-shaped semiconductor wafer W serving as a substrate,thereby heating the semiconductor wafer W. The size of the semiconductorwafer W serving as a processing target is not particularly limited, but,for example, has a diameter of 300 mm or a diameter of 450 mm. Notethat, in FIG. 1 and the views thereafter, the dimensions or numbers ofparts are illustrated to be exaggerated or simplified in accordance withneeds in order to facilitate understanding.

The heat treatment apparatus 1 is provided with a chamber 6, whichhouses the semiconductor wafer W; a flash heating unit 5, whichincorporates a plurality of flash lamps FL; and a halogen heating unit4, which incorporates a plurality of halogen lamps HL. The flash heatingunit 5 is provided in the upper side of the chamber 6, and the halogenheating unit 4 is provided in the lower side. Moreover, the heattreatment apparatus 1 is provided with, in the chamber 6, a retentionunit 7, which retains the semiconductor wafer W in a horizontalorientation, and a transfer mechanism 10, which delivers thesemiconductor wafer W between the retention unit 7 and outside of theapparatus. Furthermore, the heat treatment apparatus 1 is provided witha control unit 3, which controls the operation mechanisms provided inthe halogen heating unit 4, the flash heating unit 5, and the chamber 6and causes them to execute heat treatment of the semiconductor wafer W.

The chamber 6 is formed by attaching quartz-made chamber windows to thetop and the bottom of a tubular chamber lateral part 61. The chamberlateral part 61 has an approximately tubular shape with the open top andbottom, an upper chamber window 63 is attached to close the upperopening, and a lower chamber window 64 is attached to close the loweropening. The upper chamber window 63 constituting a ceiling part of thechamber 6 is a circular-plate-shaped member formed of quartz andfunctions as a quartz window which allows the flash light emitted fromthe flash heating unit 5 to transmit therethrough into the chamber 6.The lower chamber window 64 constituting a floor part of the chamber 6is also a circular-plate-shaped member formed of quartz and functions asa quartz window which allows the light from the halogen heating unit 4to transmit therethrough into the chamber 6.

Meanwhile, a reflection ring 68 is attached to an upper part of theinner wall surface of the chamber lateral part 61, and a reflection ring69 is attached to a lower part thereof. Both of the reflection rings 68and 69 are formed into annular shapes. The upper reflection ring 68 isattached by fitting from the upper side of the chamber lateral part 61.On the other hand, the lower reflection ring 69 is attached by fittingfrom the lower side of the chamber lateral part 61 and fixing with ascrew(s) (not shown). Therefore, both of the reflection rings 68 and 69are detachably attached to the chamber lateral part 61. The inside spaceof the chamber 6, in other words, the space surrounded by the upperchamber window 63, the lower chamber window 64, the chamber lateral part61, and the reflection rings 68 and 69 is defined as heat treatmentspace 65.

When the reflection rings 68 and 69 are attached to the chamber lateralpart 61, a recessed part 62 is formed on the inner wall surface of thechamber 6. More specifically, the recessed part 62 surrounded by thecentral part to which the reflection rings 68 and 69 are not attached onthe inner wall surface of the chamber lateral part 61, a lower endsurface of the reflection ring 68, and an upper end surface of thereflection ring 69 is formed. The recessed part 62 is annularly formedon the inner wall surface of the chamber 6 along the horizontaldirection and surrounds the retention unit 7, which retains thesemiconductor wafer W.

The chamber lateral part 61 and the reflection rings 68 and 69 areformed of metal materials (for example, stainless steel) which areexcellent in strength and heat resistance. The inner peripheral surfacesof the reflection rings 68 and 69 are formed into mirror surfaces byelectrolytic nickel plating.

A conveyance opening (furnace opening) 66 for carrying-in andcarrying-out the semiconductor wafer W to/from the chamber 6 is formedin the chamber lateral part 61. The conveyance opening 66 can beopened/closed by a gate valve 185. The conveyance opening 66 iscommunicated with and connected to the outer peripheral surface of therecessed part 62. Therefore, while the gate valve 185 opens theconveyance opening 66, the semiconductor wafer W can be carried into theheat treatment space 65 from the conveyance opening 66 through therecessed part 62, and the semiconductor wafer W can be carried out fromthe heat treatment space 65. When the gate valve 185 closes theconveyance opening 66, the heat treatment space 65 in the chamber 6becomes hermetically sealed space.

A gas supply hole(s) 81, which supplies a treatment gas to the heattreatment space 65, is formed in an upper part of the inner wall of thechamber 6. The gas supply hole 81 is formed at a position above therecessed part 62 and may be provided in the reflection ring 68. The gassupply hole 81 is communicated with and connected to a gas supplyingpipe 83 via buffer space 82, which is annularly formed in a lateral wallof the chamber 6. The gas supplying pipe 83 is connected to atreatment-gas supply source 85. A valve 84 is inserted to anintermediate part of a path of the gas supplying pipe 83. When the valve84 is opened, the treatment gas is fed from the treatment-gas supplysource 85 to the buffer space 82. The treatment gas flowed into thebuffer space 82 flows so as to spread in the buffer space 82, which hasa smaller fluid resistance than that of the gas supply hole 81, and issupplied into the heat treatment space 65 from the gas supply hole 81.As the treatment gas, hydrogen (H₂), ammonia (NH₃), nitrogen trifluoride(NF₃), fluorine (F₂), or the like mixed with nitrogen (N₂) or inert gas(He, Ar, etc.) serving as a carrier gas is used. On the other hand, agas exhaust hole(s) 86, which discharges the gaseous matter in the heattreatment space 65, is formed in a lower part of the inner wall of thechamber 6. The gas exhaust hole 86 is formed at a position below therecessed part 62 and may be provided in the reflection ring 69. The gasexhaust hole 86 is communicated with and connected to a gas exhaust pipe88 via buffer space 87, which is annularly formed in the lateral wall ofthe chamber 6. The gas exhaust pipe 88 is connected to an exhaust unit190. A valve 89 is inserted to an intermediate part of a path of the gasexhaust pipe 88. When the valve 89 is opened, the gaseous matter in theheat treatment space 65 is discharged to the gas exhaust pipe 88 fromthe gas exhaust hole 86 through the buffer space 87. the plurality ofgas supply holes 81 and the gas exhaust holes 86 may be provided alongthe circumferential direction of the chamber 6 or may have slit shapes.The treatment-gas supply source 85 and the exhaust unit 190 may be themechanisms provided in the heat treatment apparatus 1 or may beutilities of a plant in which the heat treatment apparatus 1 isinstalled.

A gas exhaust pipe 191, which discharges the gaseous matter in the heattreatment space 65, is connected also to a distal end of the conveyanceopening 66. The gas exhaust pipe 191 is connected to the exhaust unit190 via a valve 192. When the valve 192 is opened, the gaseous matter inthe chamber 6 is discharged via the conveyance opening 66.

FIG. 2 is a perspective view showing an overall appearance of theretention unit 7. The retention unit 7 includes a base ring 71, couplingparts 72, and a susceptor 74. All of the base ring 71, the couplingparts 72, and the susceptor 74 are formed of quartz. In other words, theentire retention unit 7 is formed of quartz.

The base ring 71 is a quartz member having an arc shape, which is apartially-missing annular shape. This missing part is provided in orderto prevent interference between later-described transfer arms 11 of thetransfer mechanism 10 and the base ring 71. The base ring 71 is placedon the bottom surface of the recessed part 62 and is, as a result,supported by the wall surface of the chamber 6 (see FIG. 1). Theplurality of (four in the present preferred embodiment) coupling parts72 are provided to rise from the upper surface of the base ring 71 alongthe circumferential direction of the annular shape thereof. The couplingparts 72 are also quartz members and are fixed to the base ring 71 bywelding.

The susceptor 74 is supported by the four coupling parts 72 provided onthe base ring 71. FIG. 3 is a plan view of the susceptor 74. FIG. 4 is across-sectional view of the susceptor 74. The susceptor 74 is providedwith a retention plate 75, a guide ring 76, and a plurality of substratesupport pins 77. The retention plate 75 is an approximately-circularflat-plate-shaped member formed of quartz. The diameter of the retentionplate 75 is larger than the diameter of the semiconductor wafer W. Inother words, the retention plate 75 has a larger planar size than thesemiconductor wafer W.

The guide ring 76 is installed at an upper-surface peripheral part ofthe retention plate 75. The guide ring 76 is an annular member having alarger inner diameter than the diameter of the semiconductor wafer W.For example, if the diameter of the semiconductor wafer W is 300 mm, theinner diameter of the guide ring 76 is 320 mm. The inner periphery ofthe guide ring 76 is formed into a tapered surface which is widenedupward from the retention plate 75. The guide ring 76 is formed ofquartz, which is similar to that of the retention plate 75. The guidering 76 may be welded onto the upper surface of the retention plate 75or may be fixed to the retention plate 75 with separately processed pinsor the like. Alternatively, the retention plate 75 and the guide ring 76may be processed as an integrated member.

The region of the upper surface of the retention plate 75 that is in theinside of the guide ring 76 serves as a planar retention surface 75 a,which retains the semiconductor wafer W. The plurality of substratesupport pins 77 are provided to rise from the retention surface 75 a ofthe retention plate 75. In the present preferred embodiment, in total,twelve substrate support pins 77 are provided to rise therefrom at every30° along the circumference of a concentric circle of the outercircumferential circle of the retention surface 75 a (innercircumferential circle of the guide ring 76). The diameter of the circleon which the twelve substrate support pins 77 are disposed (the distancebetween the opposed substrate support pins 77) is smaller than thediameter of the semiconductor wafer W and, if the diameter of thesemiconductor wafer W is 300 mm, is 270 mm to 280 mm (280 mm in thepresent preferred embodiment). Each of the substrate support pins 77 isformed of quartz. The plurality of substrate support pins 77 may beprovided on the upper surface of the retention plate 75 by welding ormay be integrally processed with the retention plate 75.

Returning to FIG. 2, the four coupling parts 72, which are provided torise from the base ring 71, and peripheral parts of the retention plate75 of the susceptor 74 are fixed by welding. In other words, thesusceptor 74 and the base ring 71 are fixedly coupled by the couplingparts 72. When the base ring 71 of the retention unit 7 is supported bythe wall surface of the chamber 6, the retention unit 7 is attached tothe chamber 6. In the state in which the retention unit 7 is attached tothe chamber 6, the retention plate 75 of the susceptor 74 is in ahorizontal orientation (an orientation in which the normal line thereofmatches the vertical direction). Therefore, the retention surface 75 aof the retention plate 75 becomes a horizontal surface.

The semiconductor wafer W carried into the chamber 6 is placed andretained in the horizontal orientation on the susceptor 74 of theretention unit 7 attached to the chamber 6. At this point, thesemiconductor wafer W is retained by the susceptor 74 by being supportedby the twelve substrate support pins 77, which are provided to rise fromthe retention plate 75. More strictly, upper ends of the twelvesubstrate support pins 77 contact the lower surface of the semiconductorwafer W and support the semiconductor wafer W. Since the heights of thetwelve substrate support pins 77 (the distances from the upper ends ofthe substrate support pins 77 to the retention surface 75 a of theretention plate 75) are equal, the semiconductor wafer W can besupported in the horizontal orientation by the twelve substrate supportpins 77.

The semiconductor wafer W is supported by the plurality of substratesupport pins 77 with a predetermined interval from the retention surface75 a of the retention plate 75. The thickness of the guide ring 76 islarger than the height of the substrate support pins 77. Therefore,horizontal-direction misalignment of the semiconductor wafer W, which issupported by the plurality of substrate support pins 77, is prevented bythe guide ring 76.

As shown in FIG. 2 and FIG. 3, a vertically-penetrating opening 78 isformed in the retention plate 75 of the susceptor 74. The opening 78 isprovided so that a radiation thermometer 120 (see FIG. 1) receives theradiated light (infrared light) radiated from the lower surface of thesemiconductor wafer W retained by the susceptor 74. More specifically,the radiation thermometer 120 receives the light, which is radiated fromthe lower surface of the semiconductor wafer W retained by the susceptor74, via the opening 78, and the temperature of the semiconductor wafer Wis measured by a separately-placed detector. Furthermore, in theretention plate 75 of the susceptor 74, four through holes 79, which arepenetrating therethrough for delivering the semiconductor wafer W bylater-described lift pins 12 of the transfer mechanism 10, are bored.

FIG. 5 is a plan view of the transfer mechanism 10. FIG. 6 is a lateralview of the transfer mechanism 10. The transfer mechanism 10 is providedwith the two transfer arms 11. The transfer arm 11 is formed into an arcshape, which is along the approximately-annular recessed part 62. Thetwo lift pins 12 are provided to rise from each of the transfer arms 11.Each of the transfer arms 11 is pivotable by a horizontal movementmechanism 13. The horizontal movement mechanism 13 subjects the pair oftransfer arms 11 to horizontal movement between transfer operationpositions (the positions of solid lines in FIG. 5) at which thesemiconductor wafer W is transferred with respect to the retention unit7 and escape positions (the positions of two-dot chain lines in FIG. 5)which are not overlapped with the semiconductor wafer W, which isretained by the retention unit 7, in a planar view. The horizontalmovement mechanism 13 may be one that turns the transfer arms 11respectively by individual motors or may be one that turns the pair oftransfer aims 11 in coordination by a single motor by using a linkmechanism.

The pair of transfer arms 11 are subjected to upward/downward movementby an elevating mechanism 14 together with the horizontal movementmechanism 13. When the elevating mechanism 14 moves up the pair oftransfer arms 11 at the transfer operation positions, the four lift pins12 in total pass through the through holes 79 (see FIGS. 2 and 3) boredin the susceptor 74, and the upper ends of the lift pins 12 project fromthe upper surface of the susceptor 74. On the other hand, the elevatingmechanism 14 moves down the pair of transfer arms 11 at the transferoperation positions to remove the lift pins 12 from the through holes79, and the horizontal movement mechanism 13 moves so as to open thepair of transfer arms 11; as a result, the transfer arms 11 are moved tothe escape positions. The escape positions of the pair of transfer arms11 are immediately above the base ring 71 of the retention unit 7. Sincethe base ring 71 is placed on the bottom surface of the recessed part62, the escape positions of the transfer arms 11 are in the inside ofthe recessed part 62. Also in the vicinity of the part at which a driveunit (the horizontal movement mechanism 13 and the up/down mechanism 14)of the transfer mechanism 10 is provided, an exhaust mechanism (notshown) is provided and is configured to discharge the atmosphere aroundthe drive unit of the transfer mechanism 10 to outside of the chamber 6.

Returning to FIG. 1, the flash heating unit 5 provided above the chamber6 includes, in a housing 51, light sources, which include a plurality of(30 in the present preferred embodiment) xenon flash lamps FL, and areflector 52, which is provided so as to cover the upper side of thelight sources. A lamp-light radiation window 53 is attached to a bottompart of the housing 51 of the flash heating unit 5. The lamp-lightradiation window 53 constituting a floor part of the flash heating unit5 is a plate-shaped quartz window formed of quartz. As a result ofinstalling the flash heating unit 5 above the chamber 6, the lamp-lightradiation window 53 is opposed to the upper chamber window 63. The flashlamps FL radiate flash light to the heat treatment space 65 from theupper side of the chamber 6 via the lamp-light radiation window 53 andthe upper chamber window 63.

The plurality of flash lamps FL are respectively rod-shaped lamps havinglong cylindrical shapes and are planarly arranged so that thelongitudinal directions thereof are parallel to each other along a mainsurface of the semiconductor wafer W retained by the retention unit 7(in other words, along the horizontal direction). Therefore, the planeformed by the arrangement of the flash lamps FL is also a horizontalplane.

FIG. 8 is a diagram showing a drive circuit of the flash lamp FL. Asshown in this diagram, a capacitor 93, a coil 94, the flash lamp FL, andan IGBT (insulated gate bipolar transistor) 96 are connected in series.As shown in FIG. 8, the control unit 3 is provided with a pulsegenerator 31 and a waveform setting unit 32 and is connected to an inputunit 33. As the input unit 33, various publicly-known input devices suchas a keyboard, a mouse, and a touch panel can be employed. Based on theinput contents from the input unit 33, the waveform setting unit 32 setsthe waveform of a pulse signal, and the pulse generator 31 generates thepulse signal in accordance with the waveform.

The flash lamp FL is provided with a rod-shaped glass tube (dischargetube) 92, which has a xenon gas sealed therein and disposes a positiveelectrode and a negative electrode at both ends thereof, and a triggerelectrode 91, which is attached on the outer peripheral surface of theglass tube 92. A predetermined voltage is applied to the capacitor 93 byan electric-power-source unit 95, and the capacitor 93 is charged withthe electric charge corresponding to the applied voltage (chargevoltage) thereof. A high voltage can be applied to the trigger electrode91 from a trigger circuit 97. The timing of applying the voltage to thetrigger electrode 91 by the trigger circuit 97 is controlled by thecontrol unit 3.

The IGBT 96 is a bipolar transistor incorporating a MOSFET (Metal OxideSemiconductor Field effect transistor) into a gate part and is aswitching element suitable for handling large electric power. The pulsesignal is applied to the gate of the IGBT 96 from the pulse generator 31of the control unit 3. If a voltage equal to or more than apredetermined value (High voltage) is applied to the gate, of the IGBT96, the IGBT 96 becomes an on-state; and, if a voltage less than thepredetermined value (Low voltage) is applied thereto, the IGBT 96becomes an off-state. In this manner, the drive circuit including theflash lamp FL is turned on/off by the IGBT 96. When the IGBT 96 isturned on/off, the connection to the capacitor 93 corresponding to theflash lamp FL is connected/disconnected, and the current flowing to theflash lamp FL is subjected to on/off control.

Even if the IGBT 96 becomes the on-state in a state in which thecapacitor 93 is charged and applies a high voltage to the both-endelectrodes of the glass tube 92, since the xenon gas is an electricalinsulator, electricity does not flow in the glass tube 92 in a normalstate. However, if the trigger circuit 97 applies the high voltage tothe trigger electrode 91 and breaks down insulation, discharge betweenthe both-end electrodes causes a current to instantly flow in the glasstube 92, and light is emitted by the excitation of atoms or molecules ofxenon of this process.

The drive circuit as shown in FIG. 8 is individually provided for eachof the plurality of flash lamps FL provided in the flash heating unit 5.In the present preferred embodiment, since the 30 flash lamps FL areplanarly arranged, corresponding to them, 30 drive circuits like thatshown in FIG. 8 are provided. Therefore, the currents flowing to the 30flash lamps FL, respectively, are subjected to individual on/off controlby the corresponding IGBTs 96.

Meanwhile, the reflector 52 is provided above the plurality of flashlamps FL so as to cover the entirety thereof. A basic function of thereflector 52 is to reflect the flash light, which is emitted from theplurality of flash lamps FL, to the side of the heat treatment space 65.The reflector 52 is formed of an aluminum alloy plate, and the surfacethereof (the surface on the side facing the flash lamps FL) hasundergone surface roughening processing by blast treatment.

The halogen heating unit 4 provided below the chamber 6 incorporates theplurality of (40 in the present preferred embodiment) halogen lamps HLin a housing 41. The halogen heating unit 4 is a light radiation unitwhich carries out light radiation to the heat treatment space 65 fromthe lower side of the chamber 6 via the lower chamber window 64 by theplurality of halogen lamps HL and heats the semiconductor wafer W.

FIG. 7 is a plan view showing a disposition of the plurality of halogenlamps HL. The 40 halogen lamps HL are disposed separately in upper/lowertwo levels. The 20 halogen lamps HL are disposed in the upper levelwhich is close to the retention unit 7, and the 20 halogen lamps HL aredisposed also in the lower level which is more distant from theretention unit 7 than the upper level. Each of the halogen lamps HL is arod-shaped lamp having a long cylindrical shape. Both in the upper leveland the lower level, the 20 halogen lamps HL are arranged so that thelongitudinal directions thereof are parallel to one another along themain surface of the semiconductor wafer W retained by the retention unit7 (in other words, along the horizontal direction). Therefore, both inthe upper level and the lower level, the plane formed by the arrangementof the halogen lamps HL is a horizontal plane.

As shown in FIG. 7, compared with the region opposed to a central partof the semiconductor wafer W retained by the retention unit 7, thedisposition density of the halogen lamps HL is higher in the regionopposed to a peripheral part thereof both in the upper level and thelower level. In other words, both in the upper and lower levels, thedisposition pitches of the halogen lamps HL are shorter in theperipheral part than in the central part of the lamp arrangement.Therefore, radiation with a higher light intensity can be carried outfor the peripheral part of the semiconductor wafer W in whichtemperature reduction easily occurs in a case of heating by the lightradiation from the halogen heating unit 4.

The lamp group including the halogen lamps HL of the upper level and thelamp group including the halogen lamps HL of the lower level arearranged so as to intersect with each other like a lattice. In otherwords, the 40 halogen lamps HL in total are disposed so that thelongitudinal direction of the 20 halogen lamps HL disposed in the upperlevel and the longitudinal direction of the 20 halogen lamps HL disposedin the lower level intersect with each other.

The halogen lamps HL are the light sources of a filament type in whichlight is emitted by causing a filament to be incandescent bydistributing electricity to the filament disposed in the glass tube. Inthe glass tube, a gaseous matter of an inert gas such as nitrogen orargon to which a minute amount of halogen element (iodine, bromine,etc.) is introduced is sealed. As a result of introducing the halogenelement, the temperature of the filament can be set to a hightemperature while inhibiting breaking of the filament. Therefore, thehalogen lamps HL have characteristics that the life thereof is longcompared with normal incandescent light bulbs and that strong light canbe continuously radiated. In other words, the halogen lamps HL arecontinuous lighting lamps which emit light continuously at least onesecond or more. Moreover, the halogen lamps HL have long lives sincethey are rod-shaped lamps, and, as a result of disposing the halogenlamps HL along the horizontal direction, the radiation efficiency to thesemiconductor wafer W in the upper side becomes excellent.

Also in the housing 41 of the halogen heating unit 4, a reflector 43 isprovided in the lower side of the two levels of halogen lamps HL (FIG.1). The reflector 43 reflects the light, which is emitted from theplurality of halogen lamps HL, to the side of the heat treatment space65.

The control unit 3 controls the above described various operationmechanisms, which are provided in the heat treatment apparatus 1. Theconfiguration of the control unit 3 as hardware is similar to a generalcomputer. More specifically, the control unit 3 is provided with: a CPUserving as a circuit which carries out various arithmetic processing, aROM serving as a read-only memory which stores basic programs, a RAMserving as a readable/writable memory which stores various information,and a magnetic disk which stores control software, data, etc. When theCPU of the control unit 3 executes a predetermined processing program,the process in the heat treatment apparatus 1 progresses.

Other than the above described configuration, the heat treatmentapparatus 1 is provided with various cooling structures in order toprevent excessive temperature rises of the halogen heating unit 4, theflash heating unit 5, and the chamber 6 caused by the heat energygenerated by the halogen lamps HL and the flash lamps FL in the heattreatment of the semiconductor wafer W. For example, the wall of thechamber 6 is provided with a water cooling pipe (not shown). The halogenheating unit 4 and the flash heating unit 5 have air-cooling structureswhich form gaseous flows therein and exhaust heat. Air is supplied alsoto the gap between the upper chamber window 63 and the lamp-lightradiation window 53 and cools the flash heating unit 5 and the upperchamber window 63.

Next, the manufacturing method of the semiconductor device according tothe present invention will be described. In the present preferredembodiment, first, a silicon oxide film is formed on the surface of thesemiconductor wafer W of silicon (Si), and a high-dielectric-constantgate insulating film (High-k film) is formed thereon. FIG. 9 is adiagram schematically showing a structure of the semiconductor wafer Won which the high-dielectric-constant gate insulating film is formed.

In the present preferred embodiment, before a gate is formed, ions (forexample, arsenic (As), phosphorous (P), boron (B)) are implanted into asilicon base material 101, and a source 102 and a drain 103 are formed.An interface layer film 104 of silicon dioxide (SiO₂) is formed on thesurface of the silicon base material 101 on which the source 102 and thedrain 103 are formed. The interface layer film 104 is an underlyinglayer required for maintaining good interface characteristics betweenthe high-dielectric-constant gate insulating film 105 and the siliconbase material 101. The film thickness of the interface layer film 104 ofsilicon dioxide is extremely thin and is, for example, about 1 nm. As aformation method of the interface layer film 104, for example,publicly-known various methods such as a thermal oxidation method can beemployed.

Then, the high-dielectric-constant gate insulating film 105 is fowled onthe interface layer film 104 of silicon dioxide. As thehigh-dielectric-constant gate insulating film 105, for example, ahigh-dielectric-constant material such as HfO₂, ZrO₂, Al₂O₃, La₂O₃, orthe like can be used (in the present preferred embodiment, HfO₂). Thehigh-dielectric-constant gate insulating film 105 can be fainted bydepositing the high-dielectric-constant material on the interface layerfilm 104, for example, by ALD (Atomic Layer Deposition). The filmthickness of the high-dielectric-constant gate insulating film 105deposited on the interface layer film 104 is also extremely thin and is,for example, about 1 nm. The formation method of thehigh-dielectric-constant gate insulating film 105 is not limited to ALD,and, for example, a publicly known method such as MOCVD (Metal OrganicChemical Vapor Deposition) can be employed.

Then, a metal gate electrode is further formed on thehigh-dielectric-constant gate insulating film 105. FIG. 10 is a diagramschematically showing the structure of the semiconductor wafer W onwhich the metal gate electrode is formed. Herein, in the presentpreferred embodiment, the metal gate electrode 106 containing fluorine(F) is formed on the high-dielectric-constant gate insulating film 105.The metal gate electrode 106 is formed of, for example, titanium nitride(TiN). The titanium nitride is a nitride of titanium, and titanium istypically obtained by reducing titanium tetrachloride (TiCl₄). Thetitanium nitride containing fluorine can be obtained by using a materialobtained by replacing part of chlorine of the titanium tetrachloridewith fluorine as a raw material. With such titanium nitride containingfluorine, the metal gate electrode 106 is formed on thehigh-dielectric-constant gate insulating film 105.

As a formation method of the metal gate electrode 106, for example, CVDor ALD can be used. The film thickness of the metal gate electrode 106formed on the high-dielectric-constant gate insulating film 105 is 10 nmto 20 nm. The content (concentration) of fluorine in the metal gateelectrode 106 is 0.1 at % or more to 10 at % or less.

Then, heat treatment with respect to the semiconductor wafer W on whichthe metal gate electrode 106 containing fluorine is formed is carriedout by the above described heat treatment apparatus 1. Hereinafter, theheat treatment of the semiconductor wafer W by the heat treatmentapparatus 1 will be described. A treatment procedure of the heattreatment apparatus 1 described below progresses when the control unit 3controls the operation mechanisms of the heat treatment apparatus 1.

First, the gate valve 185 is opened to open the conveyance opening 66,and the semiconductor wafer W is carried into the heat treatment space65 in the chamber 6 via the conveyance opening 66 by a conveyance robotoutside the apparatus. The semiconductor wafer W carried in by theconveyance robot moves forward to the position immediately above theretention unit 7 and stops. Then, the pair of transfer arms 11 of thetransfer mechanism 10 are horizontally moved from the escape positionsto the transfer operation position and are moved up, and, as a result,the lift pins 12 project from the upper surface of the retention plate75 of the susceptor 74 through the through holes 79 and receive thesemiconductor wafer W. In this process, the lift pins 12 are moved up tothe upper side of the upper ends of the substrate support pins 77.

After the semiconductor wafer W is placed on the lift pins 12, theconveyance robot exits from the heat treatment space 65, and theconveyance opening 66 is closed by the gate valve 185. Then, the pair oftransfer arms 11 are moved down, and, as a result, the semiconductorwafer W is passed from the transfer mechanism 10 to the susceptor 74 ofthe retention unit 7 and is retained from the lower side in a horizontalorientation. The semiconductor wafer W is retained by the susceptor 74by being supported by the plurality of substrate support pins 77, whichare provided on the retention plate 75 to rise therefrom. Thesemiconductor wafer W is retained by the retention unit 7 while thefront surface on which the high-dielectric-constant gate insulating film105 and the metal gate electrode 106 are formed serves as an uppersurface. Between a back surface of the semiconductor wafer W supportedby the plurality of substrate support pins 77 (the main surface in theopposite side of the front surface) and the retention surface 75 a ofthe retention plate 75, a predetermined interval is formed. The pair oftransfer arms 11 moved down to the lower side of the susceptor 74 arecaused to escape to the escape positions, in other words, to the insideof the recessed part 62 by the horizontal movement mechanism 13.

After the conveyance opening 66 is closed by the gate valve 185 to causethe heat treatment space 65 to be hermetically sealed space, theatmosphere in the chamber 6 is adjusted. Specifically, the valve 84 isopened, and a treatment gas is supplied from the gas supply hole 81 tothe heat treatment space 65. In the present preferred embodiment, amixed gas of hydrogen and nitrogen is supplied as the treatment gas tothe heat treatment space 65 in the chamber 6. The valve 89 is opened todischarge the gaseous matter in the chamber 6 from the gas exhaust hole86. As a result, the treatment gas supplied from the upper part of theheat treatment space 65 in the chamber 6 flows to the lower side and isdischarged from the lower part of the heat treatment space 65, and theheat treatment space 65 is replaced by the atmosphere containinghydrogen. When the valve 192 is opened, the gaseous matter in thechamber 6 is discharged also from the conveyance opening 66.Furthermore, the atmosphere around the drive unit of the transfermechanism 10 is also discharged by an exhaust mechanism (not shown).

The interior of the chamber 6 is replaced by the atmosphere containinghydrogen, and the semiconductor wafer W is retained in the horizontalorientation from the lower side by the susceptor 74; and, then, the 40halogen lamps HL of the halogen heating unit 4 are lit at the same time,and preliminary heating (assist heating) is started. The halogen lightemitted from the halogen lamps HL transmits through the lower chamberwindow 64 and the susceptor 74, which are formed of quartz, and isradiated from the back surface of the semiconductor wafer W. Byreceiving the light radiation from the halogen lamps HL, thesemiconductor wafer W is subjected to preliminary heating, and thetemperature thereof is increased. The transfer arms 11 of the transfermechanism 10 have escaped to the inside of the recessed part 62 and,therefore, do not disturb the heating by the halogen lamps HL.

When the preliminary heating by the halogen lamps HL is carried out, thetemperature of the semiconductor wafer W is measured by the radiationthermometer 120. More specifically, the infrared light radiated from theback surface of the semiconductor wafer W, which is retained by thesusceptor 74, via the opening 78 is received by the radiationthermometer 120 to measure the wafer temperature during the temperatureincrease. The measured temperature of the semiconductor wafer W istransmitted to the control unit 3. The control unit 3 monitors whetherthe temperature of the semiconductor wafer W, which is increased by thelight radiation from the halogen lamps HL, has reached a predeterminedpreliminary heating temperature T1 or not and, at the same time,controls the output of the halogen lamps HL. More specifically, thecontrol unit 3 subjects the output of the halogen lamps HL to feedbackcontrol based on the value measured by the radiation thermometer 120 sothat the temperature of the semiconductor wafer W becomes thepreliminary heating temperature T1. The preliminary heating temperatureT1 is about 350° C. to 600° C. (600° C. in the present preferredembodiment).

After the temperature of the semiconductor wafer W has reached thepreliminary heating temperature T1, the control unit 3 maintains thesemiconductor wafer W at the preliminary heating temperature T1 for awhile. Specifically, at the point of time when the temperature of thesemiconductor wafer W measured by the radiation thermometer 120 reachesthe preliminary heating temperature T1, the control unit 3 adjusts theoutput of the halogen lamps HL and maintains the temperature of thesemiconductor wafer W approximately to the preliminary heatingtemperature T1.

By carrying out such preliminary heating by the halogen lamps HL, thetemperature of the entire semiconductor wafer W is uniformly increasedto the preliminary heating temperature T1. In the stage of thepreliminary heating by the halogen lamps HL, there is a tendency thatthe temperature of the peripheral part of the semiconductor wafer W atwhich heat dissipation more readily occurs is reduced than that of thecentral part. However, the disposition density of the halogen lamps HLin the halogen heating unit 4 is higher in the region opposed to theperipheral part than the region opposed to the central part of thesemiconductor wafer W. Therefore, the light intensity radiated to theperipheral part of the semiconductor wafer W at which heat dissipationreadily occurs becomes high, and the in-plane temperature distributionof the semiconductor wafer W in the preliminary heating stage can beuniformized. Furthermore, since the inner peripheral surface of thereflection ring 69 attached to the chamber lateral part 61 is formedinto the mirror surface, the light intensity reflected by the innerperipheral surface of the reflection ring 69 toward the peripheral partof the semiconductor wafer W becomes high, and the in-plane temperaturedistribution of the semiconductor wafer W in the preliminary heatingstage can be more uniformized.

At the point of time when predetermined time has elapsed after thetemperature of the semiconductor wafer W reaches the preliminary heatingtemperature T1, flash light radiation to the front surface of thesemiconductor wafer W is carried out from the flash lamps FL of theflash heating unit 5. When the flash light radiation is to be carriedout by the flash lamps FL, electric charge is accumulated in thecapacitor 93 by the electric-power-source unit 95 in advance. Then, inthe state in which the electric charge is accumulated in the capacitor93, the pulse signal is output from the pulse generator 31 of thecontrol unit 3 to the IGBT 96 and subjects the IGBT 96 to on/off drive.

The waveform of the pulse signal can be defined by inputting, from theinput unit 33, a recipe in which the time of a pulse width(s) (on time)and the time of a pulse interval(s) (off time) are sequentially set asparameters. When such a recipe is input by an operator from the inputunit 33 to the control unit 3, in accordance with that, the waveformsetting unit 32 of the control unit 3 sets a pulse waveform whichrepeats on/off. Then, in accordance with the pulse waveform set by thewaveform setting unit 32, the pulse generator 31 outputs the pulsesignal. As a result, the pulse signal of the set waveform is applied tothe gate of the IGBT 96, and the on/off drive of the IGBT 96 iscontrolled. Specifically, when the pulse signal input to the gate of theIGBT 96 is on, the IGBT 96 becomes an on-state; and, when the pulsesignal is off, the IGBT 96 becomes an off-state.

In synchronization with the timing at which the pulse signal output fromthe pulse generator 31 becomes on, the control unit 3 controls thetrigger circuit 97 and applies a high voltage (trigger voltage) to thetrigger electrode 91. In the state in which electric charge isaccumulated in the capacitor 93, the pulse signal is input to the gateof the IGBT 96, and the high voltage is applied to the trigger electrode91 in synchronization with the timing at which the pulse signal becomeson; as a result, when the pulse signal is on, a current always flowsbetween the both end electrodes in the glass tube 92, and light isemitted by the excitation of the atoms or molecules of xenon of thisprocess.

In this manner, the 30 flash lamps FL of the flash heating unit 5 emitlight, and the flash light is radiated to the front surface of thesemiconductor wafer W retained by the retention unit 7. Herein, if theflash lamp FL is caused to emit light without using the IGBT 96, theelectric charge accumulated in the capacitor 93 is consumed in one lightemission, and the output waveform from the flash lamp FL becomes asimple single pulse having a width of about 0.1 milliseconds to 10milliseconds. On the other hand, in the present preferred embodiment,the IGBT 96 serving as the switching element is connected in thecircuit, and the pulse signal is output to the gate thereof so as toconnect/disconnect the supply of electric charge from the capacitor 93to the flash lamp FL by the IGBT 96 and on/off control of the currentwhich flows to the flash lamp FL is carried out. As a result, the lightemission of the flash lamp FL is subjected to so-called chopper control,the electric charge accumulated in the capacitor 93 is divided andconsumed, and the flash lamp FL repeats blinking in an extremely shortperiod of time. Since a next pulse is applied to the gate of the IGBT 96and increases the current value again before the current value flowingin the circuit becomes completely “0”, light-emission output does notbecome completely “0” even while the flash lamp FL is repeatingblinking.

By subjecting the current flowing to the flash lamp FL to the on/offcontrol by the IGBT 96, the light-emission pattern (time waveform oflight-emission output) of the flash lamp FL can be freely defined, andlight-emission time and light-emission intensity can be freely adjusted.The pattern of the on/off drive of the IGBT 96 is defined by the time ofthe pulse width and the time of the pulse interval input from the inputunit 33. In other words, as a result of incorporating the IGBT 96 in thedrive circuit of the flash lamp FL, the light-emission pattern of theflash lamp FL can be freely defined only by appropriately setting thetime of the pulse width and the time of the pulse interval input fromthe input unit 33.

Specifically, for example, if the ratio of the time of the pulse widthwith respect to the time of the pulse interval input from the input unit33 is increased, the current flowing to the flash lamp FL is increased,and the light-emission intensity becomes strong. Conversely, if theratio of the time of the pulse width with respect to the time of thepulse interval input from the input unit 33 is reduced, the currentflowing to the flash lamp FL is reduced, and the light-emissionintensity becomes weak. If the ratio of the time of the pulse intervaland the time of the pulse width input from the input unit 33 isappropriately adjusted, the light-emission intensity of the flash lampFL is constantly maintained. Furthermore, when the total time of thecombination of the time of the pulse width and the time of the pulseinterval input from the input unit 33 is increased, a current continuesto flow to the flash lamp FL for a comparatively long period of time,and the light-emission time of the flash lamp FL is increased. In thepresent preferred embodiment, the light-emission time of the flash lampFL is set between 0.1 milliseconds to 100 milliseconds.

In this manner, flash light is radiated to the front surface of thesemiconductor wafer W from the flash lamps FL for the radiation time of0.1 milliseconds or more to 100 milliseconds or less, and flash heatingof the semiconductor wafer W is carried out. When the extremely-shortand strong flash light having the radiation time of 0.1 milliseconds ormore to 100 milliseconds or less is radiated, the temperature of thefront surface of the semiconductor wafer W including thehigh-dielectric-constant gate insulating film 105 and the metal gateelectrode 106 is momentarily increased to a treatment temperature T2.The treatment temperature T2 which is a highest temperature (peaktemperature) reached by the front surface of the semiconductor wafer Wby the flash light radiation is 900° C. or more and, in the presentpreferred embodiment, is 1000° C. In the flash heating, the radiationtime of the flash light is an extremely short period of time of 100milliseconds or less; therefore, after the surface temperature of thesemiconductor wafer W is instantaneously increased to the treatmenttemperature T2, the surface temperature is immediately reduced to thevicinity of the preliminary heating temperature T1.

FIG. 11 is a diagram for describing a phenomenon which occurs when thesurface of the semiconductor wafer W is subjected to flash heating. Ifthe front surface of the semiconductor wafer W including thehigh-dielectric-constant gate insulating film 105 and the metal gateelectrode 106 is heated to the treatment temperature T2 of 900° C. ormore, the fluorine contained in the titanium nitride of the metal gateelectrode 106 goes over the interface with the high-dielectric-constantgate insulating film 105 and diffuses into the high-dielectric-constantgate insulating film 105. The fluorine diffused into thehigh-dielectric-constant gate insulating film 105 further diffuses intothe interface layer film 104 of silicon dioxide and reaches theinterface between the interface layer film 104 and the silicon basematerial 101.

The fluorine which has reached the interface between the interface layerfilm 104 and the silicon base material 101 terminates the dangling bondswhich have been present at the interface. As a result, the interfacestate between the interface layer film 104 and the silicon base material101 is reduced. The fluorine which has diffused in thehigh-dielectric-constant gate insulating film 105 bonds with the trapswhich are present in the high-dielectric-constant gate insulating film105 and eliminates them. As a result, the reliability of a gate stackstructure including the interface layer film 104 and thehigh-dielectric-constant gate insulating film 105 is improved.

As a result of subjecting the front surface of the semiconductor wafer Wto flash heating, post deposition annealing (PDA) of thehigh-dielectric-constant gate insulating film 105 is executed. Morespecifically, although the high-dielectric-constant gate insulating film105 which has not been subjected to particular heat treatmentimmediately after deposition contains many defects such as pointdefects, such defects are reduced when the temperature of thehigh-dielectric-constant gate insulating film 105 is increased to thetreatment temperature T2 by the flash heating.

Incidentally, the titanium nitride of the metal gate electrode 106contains not only fluorine, but also nitrogen. When the front surface ofthe semiconductor wafer W is heated to the treatment temperature T2 bythe flash heating, the nitrogen contained in the metal gate electrode106 also diffuses into the high-dielectric-constant gate insulating film105. If the nitrogen further diffuses into the interface layer film 104of silicon dioxide and reaches the interface between the interface layerfilm 104 and the silicon base material 101, interface characteristicsare adversely deteriorated. However, the diffusion of the nitrogenremains at the interface between the high-dielectric-constant gateinsulating film 105 and the interface layer film 104. It is for a reasonthat the diffusion coefficient of nitrogen is small compared with thediffusion coefficient of fluorine in silicon dioxide, and, in theextremely short period of time of 100 milliseconds or less, nitrogencannot diffuse in the interface layer film 104 and reach the interfacewith the silicon base material 101. Thus, by carrying out the heatingtreatment by the flash light radiation for the extremely short period oftime of 100 milliseconds or less, the diffusion of nitrogen whichdeteriorates the interface characteristics is inhibited, at the sametime, only the fluorine is caused to diffuse to the interface betweenthe interface layer film 104 and the silicon base material 101, reducethe interface state, and improve the reliability of the gate stackstructure.

After a predetermined period of time elapses after the flash heatingtreatment is finished, the halogen lamps IIL are turned off. As aresult, the temperature of the semiconductor wafer W is rapidly reducedfrom the preliminary heating temperature T1. Moreover, the supply ofhydrogen into the chamber 6 is stopped, only nitrogen is supplied, andthe heat treatment space 65 in the chamber 6 is replaced by a nitrogenatmosphere. The temperature of the semiconductor wafer W during thetemperature reduction is measured by the radiation thermometer 120, andthe measurement result thereof is transmitted to the control unit 3.According to the measurement result of the radiation thermometer 120,the control unit 3 monitors whether the temperature of the semiconductorwafer W has been reduced to a predetermined temperature or not. Then,after the temperature of the semiconductor wafer W is reduced to thepredetermined temperature or less, the pair of transfer arms 11 of thetransfer mechanism 10 are horizontally moved again from the escapepositions to the transfer operation positions and moved up; as a result,the lift pins 12 project from the upper surface of the susceptor 74 toreceive the heat-treated semiconductor wafer W from the susceptor 74.Subsequently, the conveyance opening 66 closed by the gate valve 185 isopened, the semiconductor wafer W placed on the lift pins 12 is carriedout by the conveyance robot outside the apparatus, and the heatingtreatment of the semiconductor wafer W in the heat treatment apparatus 1is completed.

In the present preferred embodiment, the metal gate electrode 106containing fluorine is formed on the high-dielectric-constant gateinsulating film 105 formed on the silicon base material 101 with theinterface layer film 104 of silicon dioxide sandwiched therebetween, andthe heating treatment by the flash light radiation is carried out forthe extremely short period of time of 100 milliseconds or less; as aresult, diffusion of nitrogen is inhibited, and, at the same time, onlythe fluorine can be diffused to the interface between the interfacelayer film 104 and the silicon base material 101. Since only thefluorine is diffused to the interface between the interface layer film104 and the silicon base material 101 while inhibiting the diffusion ofnitrogen which deteriorates the interface characteristics, the interfacestate is reduced, and the reliability of the gate stack structure can beimproved. The flash-light radiation time of the flash lamps FL can beappropriately adjusted within the range of 0.1 milliseconds or more to100 milliseconds or less.

Moreover, since the fluorine is diffused from the metal gate electrode106 containing the fluorine to the high-dielectric-constant gateinsulating film 105 and the interface layer film 104 by the heatingtreatment of the extremely short period of time, without damaging adevice structure formed on the semiconductor wafer W, the fluorine canbe introduced to the device structure.

Moreover, since the flash heating treatment of the semiconductor wafer Wis carried out in the atmosphere containing hydrogen, the diffusion rateof fluorine in the interface layer film 104 of silicon dioxide becomesfast, and fluorine can be more reliably introduced to the interfacebetween the interface layer film 104 and the silicon base material 101.

Hereinabove, the preferred embodiment of the present invention has beendescribed. However, various changes can be made other than thosedescribed above as long as the present invention does not depart fromthe gist thereof. For example, although the metal gate electrode 106 isfoamed of titanium nitride in the above described preferred embodiment,but is not limited thereto, and it may be formed of tantalum nitride(TaN), aluminum nitride (AlN), or the like. Even if the metal gateelectrode 106 is formed of tantalum nitride or aluminum nitride, byforming the metal gate electrode 106 containing fluorine on thehigh-dielectric-constant gate insulating film 105 and carrying out flashheating treatment, as well as the above described preferred embodiment,only fluorine can be diffused to the interface between the interfacelayer film 104 and the silicon base material 101 while inhibitingdiffusion of nitrogen.

Meanwhile, instead of the metal gate electrode 106, a thin filmcontaining fluorine may be formed on the high-dielectric-constant gateinsulating film 105, and flash heating treatment may be carried out.Also in this case, fluorine is diffused to the high-dielectric-constantgate insulating film 105 and the interface layer film 104 to reduce theinterface state between the interface layer film 104 and the siliconbase material 101, and the reliability of the gate stack structure canbe improved.

Meanwhile, in the above described preferred embodiment, the flashheating treatment is carried out to carry out the post depositionannealing of the high-dielectric-constant gate insulating film 105 incombination after the metal gate electrode 106 containing fluorine isformed. However, instead of this, the post deposition annealing of thehigh-dielectric-constant gate insulating film 105 may be carried outbefore the metal gate electrode 106 is formed.

Meanwhile, in the above described preferred embodiment, the flashheating treatment of the semiconductor wafer W is carried out in theatmosphere containing hydrogen. However, it is not limited thereto, andthe flash heating treatment may be carried out in an atmospherecontaining ammonia (NH₃), nitrogen trifluoride (NF₃), fluorine (F₂), orthe like. In other words, the flash heating treatment of thesemiconductor wafer W may be carried out in the gas atmosphere of oneselected from a group consisting of hydrogen, ammonia, nitrogentrifluoride, and fluorine.

If the flash heating treatment is carried out in the atmospherecontaining hydrogen as described above, the diffusion rate of fluorinein the interface layer film 104 of silicon dioxide can be increased.Meanwhile, if the flash heating treatment is carried out in theatmosphere containing ammonia or nitrogen trifluoride, nitrogen in thehigh-dielectric-constant gate insulating film 105 can be compensatedfor. Furthermore, if the flash heating treatment is carried out in theatmosphere containing fluorine, fluorine can be compensated for in acase in which the supply of fluorine only from the metal gate electrode106 is not sufficient.

Meanwhile, the heat treatment of the semiconductor wafer W is carriedout by the flash light radiation from the flash lamps FL in the abovedescribed preferred embodiment. However, it is not limited thereto, andthe heat treatment is only required to be heating treatment of 100milliseconds or less and may be carried out by, for example, laserannealing.

Meanwhile, the device structure serving as an application target of thetechniques according to the present invention is not limited to planarFET, but may be a FET of a Fin structure.

Meanwhile, the flash heating unit 5 is provided with the 30 flash lampsFL in the above described preferred embodiment. However, it is notlimited thereto, and the number of the flash lamps FL may be anarbitrary number. Meanwhile, the flash lamps FL are not limited to xenonflash lamps, but may be krypton flash lamps. Meanwhile, the number ofthe halogen lamps HL provided in the halogen heating unit 4 is notlimited to 40, but may be an arbitrary number.

Meanwhile, the semiconductor wafer W is subjected to the preliminaryheating by the halogen light radiation from the halogen lamps HL in theabove described preferred embodiment. However, the method of thepreliminary heating is not limited thereto, and the semiconductor waferW may be subjected to preliminary heating by placing it on a hot plate.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A manufacturing method of a semiconductor deviceof forming a high-dielectric-constant gate insulating film on a siliconsubstrate with an interface layer film sandwiched therebetween, themanufacturing method comprising following steps of: (a) forming thehigh-dielectric-constant gate insulating film on a surface of saidsubstrate with the interface layer film of silicon dioxide sandwichedtherebetween; (b) forming a film containing fluorine on saidhigh-dielectric-constant gate insulating film; and (c) subjecting saidsubstrate to heating treatment of 100 milliseconds or less to diffusethe fluorine to said high-dielectric-constant gate insulating film andsaid interface layer film.
 2. The manufacturing method of thesemiconductor device according to claim
 1. wherein the film formed insaid step (b) is a metal gate electrode.
 3. The manufacturing method ofthe semiconductor device according to claim 2, wherein said metal gateelectrode contains TiN, TaN, or AlN.
 4. The manufacturing method of thesemiconductor device according to claim 2, wherein a content of thefluorine contained in said metal gate electrode is 0.1 at % or more to10 at % or less.
 5. The manufacturing method of the semiconductor deviceaccording to claim 1, wherein, in said step (c), flash light is radiatedfrom a flash lamp to the surface of said substrate.
 6. The manufacturingmethod of the semiconductor device according to claim 1, wherein, insaid step (c), the heating treatment of said substrate is carried out ina gas atmosphere of one selected from a group consisting of hydrogen,ammonia, nitrogen trifluoride, and fluorine.